HIGH🇵🇱 Wersja polska

CVE-2025-0647

CVSS 7.9v3.1pub. 2026-01-14upd. 2026-01-26

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

CVSS Vector
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N

  • Arm C1 Premium

    HW
    Arm
    all versions

  • Arm C1 Premium Firmware

    OS
    Arm
    all versions

  • Arm C1 Ultra

    HW
    Arm
    all versions

  • Arm C1 Ultra Firmware

    OS
    Arm
    all versions

  • Arm Cortex A710

    HW
    Arm
    all versions

  • Arm Cortex A710 Firmware

    OS
    Arm
    all versions

  • Arm Cortex X2

    HW
    Arm
    all versions

  • Arm Cortex X2 Firmware

    OS
    Arm
    all versions

  • Arm Cortex X3

    HW
    Arm
    all versions

  • Arm Cortex X3 Firmware

    OS
    Arm
    all versions

  • Arm Cortex X4

    HW
    Arm
    all versions

  • Arm Cortex X4 Firmware

    OS
    Arm
    all versions

  • Arm Cortex X925

    HW
    Arm
    all versions

  • Arm Cortex X925 Firmware

    OS
    Arm
    all versions

  • Arm Neoverse N2

    HW
    Arm
    all versions

  • Arm Neoverse N2 Firmware

    OS
    Arm
    all versions

  • Arm Neoverse V2

    HW
    Arm
    all versions

  • Arm Neoverse V2 Firmware

    OS
    Arm
    all versions

  • Arm Neoverse V3

    HW
    Arm
    all versions

  • Arm Neoverse V3ae

    HW
    Arm
    all versions

  • Arm Neoverse V3ae Firmware

    OS
    Arm
    all versions

  • Arm Neoverse V3 Firmware

    OS
    Arm
    all versions
🔵
CHECK WITH VENDOR
No clear patch data available. Check vendor references.
CWE
References

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